There are many applications in which it is necessary to combine unsynchronized data streams from different clock domains for subsequent processing by the same device. For example, in many communication devices (e.g., switches, routers, transceivers) a single digital signal processor (DSP) may be used to process multiple packet-based input serial data streams from unsynchronized clock domains. If the input streams are handled separately, the DSP incurs a delay whenever the DSP switches between domains and the input serial data stream in the new domain is not yet completely received. Conventional solutions to such problems often require synchronization of the clocks in the different clock domains.
Therefore, there is a need in the art for improved interface circuits for combining two or more input serial data streams from unsynchronized clock domains into a single contiguous output data stream. In particular, there is a need for an interface circuit that is capable of multiplexing together two or more input serial data streams without adding special timing synchronization circuitry.